Background of the invention is the generation, adjustment and control of body bias voltages in silicon-on-insulator (SOI) CMOS technologies. An overview of the Silicon-on-Insulator (SOI) CMOS technologies is exemplary published in R. Carter et al., “22 nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications,” 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, Calif., 2016, pp. 2.2.1-2.2.4. doi: 10.1109/IEDM.2016.7838029. These technologies allow the threshold voltages of transistors to be adjusted by applying a body bias voltage or back-gate voltage. An investigation of the impact of back gate biasing schemes on energy and robustness can be found in G. de Streel and D. Bol, “Impact of back gate biasing schemes on energy and robustness of ULV logic in 28 nm UTBB FDSOI technology,” in Proc. IEEE Int. Symp. Low Power Electron. Design (ISLPED), September 2013, pp. 255-260.
Fully depleted silicon-on-insulator (FD-SOI) CMOS technologies allow the adaptation of the threshold voltages of transistors by adjusting one or more bias voltages. These bias voltages are typically applied through regions below the SOI isolation layer, sometimes called “back gates”. The scheme is known as back biasing. To an extent, a similar control of transistors' threshold voltages through biasing can be done in conventional SOI and bulk CMOS technologies, and is then also referred to as “body biasing”.
Adaptation of the threshold voltages through biasing can be done during operation of the circuit, in order to compensate variations in the fabrication process (P), of the supply voltage (V) and of the temperature (T), in an attempt to achieve a target delay time and/or target leakage current consumption. Adaptation of the threshold voltages through biasing is also a means to adjust an adaptive compromise between switching speed and leakage current consumption in order to adapt the circuit or system with regard to the performance requirement.
Hence, the adaptive back biasing (or body biasing) allows the system to adapt to changing requirements in terms of performance, operating speed, and current consumption. A multiprocessor system with a body bias control circuit can be found in U.S. Pat. No. 8,112,754 B2.
Typically, two different control voltages are used to independently control nmos transistors and pmos transistors. In general, the scheme applies to one or more control voltages.
These control voltages can be generated by charge pumps or by other controllable means. The problem is to control the voltage generation in a closed loop in such a way that the above-mentioned goals are achieved. The problem is complicated, because couplings exist between the different parts of the integrated circuit, which have to receive different control voltages. Any change in the control voltages requires a significant charge transport to the bias voltage network (e.g. implant wells). The time required for this depends on the capacitance of the control circuit powered parts of the integrated circuit. Therefore, it depends directly on the chip area of the circuit. And finally, hardware performance monitor circuits used to detect the effect of the control voltage require time for detection. A hardware performance monitor is a circuit that monitors certain parameters of certain circuit components and produces an according output signal. In a typical implementation, a hardware performance monitor can be realized as a ring oscillator, whose output signal frequency depends on the switching speed of specific logic elements. Such a hardware performance monitor can also be readout through a counter circuit, which then produces a digital output value that depends on the output signal frequency of the hardware performance monitor. For flexible use it is furthermore desirable that as little requirements are made with respect to the number and frequency of clock signals and other control signals of hardware performance monitors and corresponding read-out circuits. It is also desirable to use as little energy as possible for the generation of the control voltages, the regulation thereof and for the detection of the operating state of the controlled circuit.
Until now, hardware performance monitors in the form of delay lines are used in order to detect the effect of the control voltages. This is described in Joan Mauricio and Francesc Moll: “Local Variations Compensation with DLL-based Body Bias Generator for UTBB FD-SOI technology”, 13th International New Circuits and Systems Conference (NEWCAS), 2015 IEEE, ISBN: 978-1-4799-8893-8, whereas the control voltages are generated by charge pumps, which are controlled in a closed loop. The above-described solution has the disadvantage that it requires an external periodic reference signal whose pulse duration must be exactly matched to the desired target performance. The setting of the gain of the control loop must be set by the frequency of this external reference signal. The frequency of the reference signal therefore also depends on the area of the supplied circuit hence this solution is not very flexible.
In Milovan Blagojević et al. “A Fast, Flexible, Positive and Negative Adaptive Body-Bias Generator in 28 nm FDSOI”, 2016 IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 60-61 also a charge pump is used. The generation of the control voltages is controlled in a closed loop. The gain in the control loop can be switched between only two values. The drawback is that the concrete values for the control voltages must be specified externally. The closed control loop then ensures that the externally specified voltage values are maintained within certain tolerances. The gain factor in the control loop must be switched between the two possible values by means of an external control signal.
It is therefore one object of the invention to efficiently generate and regulate the control voltages for active body biasing such that the parts of the integrated circuit supplied with said control voltages achieve set criteria with respect to certain parameters, such as performance, speed, power consumption or other parameters. The control voltages ay assume positive and negative values relative to the reference potential of the integrated circuit and can be a multiple of the operating voltage of the integrated circuit.
Furthermore, the only external reference signal should be a clock signal with a constant frequency, the constant frequency should be selectable within wide limits. Other reference signals, e.g. voltages, currents, or other properties of a clock signal, e.g. such as pulse-width or duty cycle should neither be used nor required.
Another object is that the generation and maintenance of the control voltages should be realized with the smallest possible power consumption.